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Five Day Faculty Development Program on
Custom IC Design and ASIC Implementation using Cadence EDA Tools
28th November – 2nd December, 2016

Sponsored by TEQIP II SC 1.2

In Collaboration with ENTUPLE Technologies

For more details:

 
Organized by:
Department of
Electronics & Communication Engineering
V.R.Siddhartha Engineering College
 
Co-Ordinator:

Mr. G. Kishore Kumar
Asst. Prof, ECE
Mobile: +91-9951108777
E-Mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it

Mr. T Rajasekhar
Asst. Prof, ECE
E-Mail: This e-mail address is being protected from spambots. You need JavaScript enabled to view it
Mobile: +91-9441807539

The semester end examinations of 2nd year B.Tech regular & supplementary are scheduled on 16-04-2018 are postponed to 23-04-2018 inview of state bandh || UGC, New Delhi extended Autonomous status up to 2027-28